1. Field of the Invention
The present disclosure relates to nonvolatile memory and, more particularly, to nonvolatile memory devices and methods of fabricating the same.
2. Description of the Related Art
Generally, semiconductor memory devices are divided into volatile memories and nonvolatile memories. The volatile memories, including chiefly random access memories (RAM) such as dynamic random access memories (DRAM) and static random access memories (SRAM), retain their memory data when the power is turned on, but lose the stored data when the power is turned off. In contrast, the nonvolatile memories, including chiefly read only memories (ROM), retain their memory data even after the power is turned off.
The nonvolatile memories may be subdivided into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM).
From the view point of process technology, the nonvolatile memories may be divided into a floating gate family and a metal insulator semiconductor (MIS) family comprising a multi-layer of two or more dielectrics. The memory devices of the floating gate family use potential wells to achieve memory characteristics. For instance, EPROM tunnel oxide (ETOX) structures and split gate structures are widely applied to flash EEPROM. The split gate structure comprises two transistors in one cell. On the other hand, the memory devices of the MIS family perform memory functions by using traps positioned on a dielectric bulk, the interface between dielectrics, and the interface between the dielectric and the semiconductor. At present, the MONOS (metal oxide nitride oxide semiconductor)/SONON (semiconductor oxide nitride oxide semiconductor) structure is chiefly being employed for flash EEPROM.
FIG. 1 is a cross-sectional view of a flash memory cell structure formed by a related art technology. Referring to FIG. 1, a gate oxide layer 12 is deposited on a semiconductor substrate 10 having at least one device isolation layer 11. A first polysilicon layer 13 is deposited on the gate oxide layer 12. The first polysilicon layer 13 is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are sequentially deposited on the first polysilicon layer 13. The second polysilicon layer 16 is used as a control gate. A metal layer 17 and a nitride layer 18 are sequentially deposited on the second polysilicon layer 16. A cell structure is patterned to complete a flash memory cell by removing some portion of the gate oxide layer 12, the first polysilicon layer 13, the dielectric layer 15, the second polysilicon layer 16, the metal layer 17, and the nitride layer 18.
The above-mentioned flash memory cell has a flat-plate type floating gate and a control gate. Generally, in a flash memory, an electric potential of a control gate has to be thoroughly transferred to a floating gate to enhance the erase and program characteristics of a device. Specifically, when a flash memory performs a program function using hot carriers, the voltages of 0V, 5V, and 9V are applied to a source, a drain, and a control gate, respectively. If the voltage applied to the control gate is thoroughly transferred in a gate oxide via a floating gate and forms an electric field, hot electrons are more rapidly transferred into the floating gate. Contrarily, when the flash memory performs an erase function, the voltages of −7V and 5V are applied to the control gate and the source, respectively. In this case, electrons in the floating gate move toward the source by Fowler-Nordheim (F-N) tunneling. If the capacitance between the control gate and the floating gate is high and the capacitance between the floating gate and a substrate is low, the voltage of the floating gate is maintained at an even lower value. Therefore, more electrons move toward the source to increase the erase speed. In conclusion, in performing program or erase function, the smaller the voltage difference between a floating gate and a control gate becomes, the faster the operation speed of a flash memory becomes.
To improve program and erase characteristics of a semiconductor device, a method of using a material with high dielectric constant as a dielectric layer between a floating gate and a control gate has been suggested. However, the suggested method is being developed at present and requires more technical development.
A simple multi-layered ETOX cell structure is the simplest structure and can achieve a small cell in size. The ETOX cell structure, however, has a shortcoming that an effective cell size greatly increases because drain contacts have to be formed along a bit line. The simple multi-layered cell may have a very small size compared to other cell structures if those drain contacts are eliminated. On the other hand, from the viewpoint of device functionality, the cell malfunctions since an over erase must be controlled and the disturbance during program operation must be adjusted. In addition, because erase operation is performed through a silicon substrate, a source, or a drain, the reliability of a thin oxide layer must be ensured.
In a split gate structure cell, a select transistor without a floating gate and a storage transistor with a floating gate are serially connected. By having such an additional select transistor, the size of a unit cell becomes larger. Moreover, the cell size may considerably increase because a process margin is secured to self-align each gate and each channel of the select transistor and the storage transistor. However, from the viewpoint of device functionality, by using the additional select transistor, cell malfunctions due to an over erase can be prevented because the cell can be turned off by the select transistor, even if it is over erased. In addition, program disturbances can be prevented because a reverse program, in which a source region and a drain region are reversed due to asymmetric structure, is obviated.
However, in the split gate structure cell, junctions have to be preformed because a word line is formed in the same direction with that of active regions. In this case, a silicide process to reduce junction resistance cannot be performed because the junctions are formed by ion implantation and gates are then formed.